Datasheet4U Logo Datasheet4U.com

L9A0212 - Microprocessor

Description

of the major components of the LR4102, as shown in Figure 1.

The CPU performs all arithmetic, logical, shift, and address calculations.

The CPU supports EJTAG debug and is closely coupled with the FastMDU.

Features

  • Components.
  • Caches.
  • 16 Kbytes of two-way set-associative I-Cache 8 Kbytes of direct-mapped D-Cache.
  • R3000 MIPS CPU executes MIPS II and MIPS16 instructions 32-bit FBus, a fast demultiplexed multimaster bus, with built in control of:.
  • RAM, EPROM, or similar simple devices DRAM and SDRAM General-purpose I/O.
  • Clock module with integrated PLL and programmable clock speeds Technology.
  • LSI Logic G11.

📥 Download Datasheet

Datasheet preview – L9A0212

Datasheet Details

Part number L9A0212
Manufacturer LSI
File Size 357.89 KB
Description Microprocessor
Datasheet download datasheet L9A0212 Datasheet
Additional preview pages of the L9A0212 datasheet.

📁 Similar Datasheet

Other Datasheets by LSI

    Full PDF Text Transcription

    Click to expand full text
    TinyRISC® LR4102 Microprocessor Datasheet The TinyRISC LR4102 Microprocessor is a compact, high performance 32-bit microprocessor implemented in the LSI Logic G11™ technology. The LR4102 is a complete microprocessor solution with caches, an external bus interface with built-in memory controllers, and on-chip debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem, available to customers through the LSI Logic CoreWare® program. The LR4102 provides a 32-bit FBusMACRO to control all off-chip data transactions (including DRAM or SDRAM) and an EJTAG interface for on-chip debug with PC trace output. Figure 1 illustrates the LR4102 chip. Figure 1 LR4102 LR4102 Block Diagram MMU www.DataSheet4U.
    Published: |