LS7083N Datasheet | LSI

FEATURES : - x1 and x4 mode selection - Up to 16MHz output clock frequency - Programmable output clock pulse width - On-chip filtering of inputs for optical or magnetic encoder applications. - TTL and CMOS patible I/Os - +3V to +12V operation (VDD - VSS) - LS7083N, LS7084N (DIP); LS7083NS, LS7084NS (SOIC) - See Figure 1 Applications: - Interface incremental encoders to Up / Down Counters (See Figure 6A and Figure 6B) - Interface rotary encoders to Digital Potentiometers (See Figure 7) DESCRIPTION : The LS7083N and LS7084N are CMOS quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083N or LS7084N, are converted to strings of Up Clocks and Down Clocks ( LS7083N) or to a Clock and an Up/Down direction control (LS7084N). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION : RBIAS (Pin 1) Input for external ponent connection. A resistor connected between this input and VSS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A, B pulse separation (TOW ≤ TPS). VDD (Pin 2) Supply Voltage positive terminal. VSS (Pin 3) Supply Voltage negative terminal. A (Pin 4) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. B (Pin 5) Quadrature Clock Input B. This input has a filter circuit identical to input A. Mode (Pin 6) Mode is a 3-state input to select resolutions x1, x2 or x4. The selected resolution multiplies the input quadrature clock rate by 1, 2 and 4, respectively, in producing the outputs UPCK / DNCK and CLK (see Figure 2). The Mode input logic levels selects resolutions as follows: Logic 0 = x1 Float = x2 Logic 1 = x4 PIN ASSIGNMENT - TOP VIEW LS7083N LSI RBIAS 1 VDD (+V ) 2 VSS (-V ) 3 A4 8 UPCK 7 DNCK 6 MODE 5B LS7084N LSI RBIAS 1 VDD (+V ) 2 VSS...