LS7366R Datasheet | LSI

FEATURES : - Operating voltage: 3V to 5.5V (VDD - VSS) - 5V count frequency: 40MHz - 3V count frequency: 20MHz - 32-bit counter (CNTR). - 32-bit data register (DTR) and parator. - 32-bit output register (OTR). - Two 8-bit mode registers (MDR0, MDR1) for programmable functional modes. - 8-bit instruction register (IR). - 8-bit status register (STR). - Latched Interrupt output on Carry or Borrow or pare or Index. - Index driven counter load, output register load or counter reset. - Internal quadrature clock decoder and filter. - x1, x2 or x4 mode of quadrature counting. - Non-quadrature up/down counting. - Modulo-N, Non-recycle, Range-limit or Free-running modes of counting - 8-bit, 16-bit, 24-bit and 32-bit programmable configuration synchronous (SPI) serial interface - LS7366R (DIP), LS7366R-S (SOIC), LS7366R-TS (TSSOP) - See Figure 1 SPI/MICROWIRE (Serial Peripheral Interface): - Standard 4-wire connection: MOSI, MISO, SS/ and SCK. - Slave mode only. GENERAL DESCRIPTION : LS7366R is a 32-bit CMOS counter, with direct interface for quadrature clocks from incremental encoders. It also interfaces with the index signals from incremental encoders to perform variety of marker functions. For munications with microprocessors or microcontrollers, it provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os are SS/, SCK, MISO and MOSI. The data transfer between a microcontroller and a slave LS7366R is synchronous. The synchronization is done by the SCK clocks supplied by the microcontroller. Each transmission is organized in blocks of 1 to 5 bytes of data. A transmission cycle is intitiated by a high to low transition of the SS/ input. The first byte received in a transmission cycle is always an instruction byte, whereas the second through the fifth bytes are always interpreted as data bytes. A transmission cycle is terminated with the low to high transition of the SS/ input. Received bytes are shifted in at the MOSI input, MSB first, with the leading edges (high...