Datasheet4U Logo Datasheet4U.com

5256VA - In-System Programmable 3.3V SuperWIDE High Density PLD

General Description

The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs.

Key Features

  • SuperWIDE HIGH.

📥 Download Datasheet

Datasheet Details

Part number 5256VA
Manufacturer Lattice Semiconductor
File Size 311.45 KB
Description In-System Programmable 3.3V SuperWIDE High Density PLD
Datasheet download datasheet 5256VA Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
525-01 USER CONFIGURABLE CLOCK Renesas
525-02 USER CONFIGURABLE CLOCK Renesas
52505C Common Mode Chokes muRata
5252 Hash RF Chokes Bourns
52520-xxxx CONNECTOR FCI

Other Datasheets by Lattice Semiconductor

Part Number Description

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ispLSI 5256VA ® In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 192 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns — TTL/3.3V/2.