GAL18V10 Overview
The GAL18V10, at 7.5 ns maximum propagation delay time, bines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when pared to its bipolar counterparts. The E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly...
GAL18V10 Key Features
- HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 7.5 ns Maximum Propagation Delay
- Fmax = 111 MHz
- 5.5 ns Maximum from Clock Input to Data Output
- TTL patible 16 mA Outputs
- UltraMOS® Advanced CMOS Technology
- LOW POWER CMOS
- 75 mA Typical Icc
- ACTIVE PULL-UPS ON ALL PINS
- E2 CELL TECHNOLOGY