GAL20RA10
Overview
The GAL20RA10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor’s E2CMOS circuitry achieves power levels as low as 75mA typical ICC which represents a substantial savings in power when compared to bipolar counterparts.
- HIGH PERFORMANCE E2CMOS ® TECHNOLOGY - 7.5 ns Maximum Propagation Delay - Fmax = 83.3 MHz - 9 ns Maximum from Clock Input to Data Output - TTL Compatible 8 mA Outputs - UltraMOS® Advanced CMOS Technology
- 50% to 75% REDUCTION IN POWER FROM BIPOLAR - 75mA Typical Icc
- ACTIVE PULL-UPS ON ALL PINS
- E CELL TECHNOLOGY - Reconfigurable Logic - Reprogrammable Cells - 100% Tested/100% Yields - High Speed Electrical Erasure (<100 ms) - 20 Year Data Retention
- TEN OUTPUT LOGIC MACROCELLS - Independent Programmable Clocks - Independent Asynchronous Reset and Preset - Registered or Combinatorial with Polarity - Full Function and Parametric Compatibility with PAL20RA10
- PRELOAD AND POWER-ON RESET OF ALL REGISTERS - 100% Functional Testability
