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GAL20XV10 - High-Speed E2CMOS PLD Generic Array Logic

General Description

The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market.

Key Features

  • HIGH.

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Datasheet Details

Part number GAL20XV10
Manufacturer Lattice Semiconductor
File Size 234.09 KB
Description High-Speed E2CMOS PLD Generic Array Logic
Datasheet download datasheet GAL20XV10 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic™ Features • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 90mA Maximum Icc — 75mA Typical Icc • ACTIVE PULL-UPS ON ALL PINS • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100 ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4 — Registered or Combinatorial with Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS • APPLICATIONS INC