ISPCLOCK5316S Datasheet In-system Programmable Zero-delay

Manufacturer: Lattice Semiconductor

Overview: ispClock 5300S Family ™ In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	ISPCLOCK5316S
Manufacturer	Lattice Semiconductor
File Size	1.28 MB
Description	In-System Programmable Zero-Delay
Datasheet	ISPCLOCK5316S ISPCLOCK5300S Datasheet (PDF)

Four Operating Conﬁgurations.
Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider.
Up to +/- 5ns skew range.
Coarse and ﬁne adjustment modes.
Up to Three Clock Frequency Domains.
Flexible Clock Reference and External Feedback Inputs.
Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL,.

Part Number	Description
ISPCLOCK5312S	In-System Programmable Zero-Delay
ISPCLOCK5300S	In-System Programmable Zero-Delay
ISPCLOCK5304S	In-System Programmable Zero-Delay
ISPCLOCK5308S	In-System Programmable Zero-Delay
ISPCLOCK5320S	In-System Programmable Zero-Delay
ispClock5400D	Zero Delay And Fan-Out Buffer
ispClock5406D	Zero Delay And Fan-Out Buffer
ispClock5410D	Zero Delay And Fan-Out Buffer
ISPCLOCK5500	In-System Programmable Zero-Delay
ISPCLOCK5510	In-System Programmable Zero-Delay