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ISPGAL22V10 Datasheet In-system Programmable E2cmos Pld

Manufacturer: Lattice Semiconductor

Overview: Specifications ispGAL22V10 ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array.

General Description

PIN CONFIGURATION The ispGAL22V10, at 7.5ns maximum propagation delay time, bines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device.

E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.

Key Features

  • IN-SYSTEM.

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