ISPL1048E-50LT Datasheet | Lattice Semiconductor

eatures - HIGH DENSITY PROGRAMMABLE LOGIC - 8,000 PLD Gates - 96 I/O Pins, Twelve Dedicated Inputs - 288 Registers - High-Speed Global Interconnects - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. - Small Logic Block Size for Random Logic - Functionally and Pin-out patible to isp LSI 1048C TECHNOLOGY - HIGH PERFORMANCE - fmax = 125 MHz Maximum Operating Frequency - tpd = 7.5 ns Propagation Delay - TTL patible Inputs and Outputs - Electrically Eraseable and Reprogrammable - Non-Volatile - 100% Tested at Time of Manufacture - IN-SYSTEM PROGRAMMABLE - In-System Programmable (ISP™) 5V Only - Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality - Reprogram Soldered Devices for Faster Prototyping - OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS - plete Programmable Device Can bine Glue Logic and Structured Designs - Enhanced Pin Locking Capability - Four Dedicated Clock Input Pins - Synchronous and Asynchronous Clocks - Programmable Output Slew Rate Control to Minimize Switching Noise - Flexible Pin Placement - Optimized Global Routing Pool Provides Global Interconnectivity - isp LSI DEVELOPMENT TOOLS isp VHDL™ Systems - VHDL/Verilog-HDL/Schematic Design...