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ispLSI ® 1024EA
In-System Programmable High Density PLD
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates — 48 I/O Pins, Two Dedicated Inputs — 144 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
• NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User Selectable 3.3V or 5V I/O Supports MixedVoltage Systems (VCCIO Pin) — Open-Drain Output Option
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 200 MHz Maximum Operating Frequency — tpd = 4.
ISPLSI1024EA Datasheet
