Lattice Semiconductor ISPLSI2032VL
The ispLSI 2032VL is a High Density Programmable Logic Device containing 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable.| Part No. | ISPLSI2032VL |
|---|---|
| Datasheet | ISPLSI2032VL Download |
| Manufacturer |  Lattice Semiconductor |
| Description | 2.5V In-System Programmable SuperFAST High Density PLD |
| Buy | Stock & Price |
FEATURES
● SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V and 2032VE Devices● 2.5V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 45 mA Typical Active Current
● HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
● IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration...
