ISPLSI3256E Datasheet | Lattice Semiconductor

Features - HIGH-DENSITY PROGRAMMABLE LOGIC - 256 I/O Pins - 12000 PLD Gates - 512 Registers - High Speed Global Interconnect - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. - Small Logic Block Size for Random Logic - HIGH PERFORMANCE E2CMOS® TECHNOLOGY - fmax = 100 MHz Maximum Operating Frequency - tpd = 10 ns Propagation Delay - TTL patible Inputs and Outputs - Electrically Erasable and Reprogrammable - Non-Volatile - 100% Tested at Time of Manufacture - Unused Product Term Shutdown Saves Power - IN-SYSTEM PROGRAMMABLE - 5V In-System Programmable (ISP™) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol - Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality - Reprogram Soldered Devices for Faster Debugging - 100% IEEE 1149.1 BOUNDARY SCAN PATIBLE - OFFERS THE EASE OF USE AND FAST...