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ISPXPGA200E - eXpanded Programmable Logic Device

Download the ISPXPGA200E datasheet PDF. This datasheet also covers the ISPXPGA200 variant, as both devices belong to the same expanded programmable logic device family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • required for today’s system-level design. The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the sysHSI Block. Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ISPXPGA200-LatticeSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ISPXPGA200E
Manufacturer Lattice Semiconductor
File Size 839.02 KB
Description eXpanded Programmable Logic Device
Datasheet download datasheet ISPXPGA200E Datasheet

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Other Datasheets by Lattice Semiconductor

Part Number Description
ISPXPGA200 eXpanded Programmable Logic Device
ISPXPGA1200 eXpanded Programmable Logic Device
ISPXPGA1200E eXpanded Programmable Logic Device
ISPXPGA125 eXpanded Programmable Logic Device
ISPXPGA125E eXpanded Programmable Logic Device

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
February 2010 Includes High- Performance, Low-Cost “E-Series” ispXPGA® Family Data Sheet DS1026 DISSECLOENCTTINDUEEVIDCES  Non-volatile, Infinitely Reconfigurable • Instant-on - Powers up in microseconds via • Microprocessor configuration interface • Program E2CMOS while operating from SRAM on-chip E2CMOS® based memory • No external configuration memory  Eight sysCLOCK™ Phase Locked Loops (PLLs) for Clock Management • Excellent design security, no bit stream to intercept • True PLL technology • Reconfigure SRAM based logic in milliseconds • 10MHz to 320MHz operation  High Logic Density for System-level • Clock multiplication and division Integration • Phase adjustment • 139K to 1.25M functional gates • Shift clocks in 250ps steps • 160 to 496 I/O • 1.8V, 2.5V, and 3.