LFEC10 Datasheet | Lattice Semiconductor

Features - Extensive Density and Package Options - 1.5K to 41K LUT4s - 65 to 576 I/Os - Density migration supported - - - - - - LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL SSTL 3/2 Class I, II, SSTL18 Class I HSTL 18 Class I, II, III, HSTL15 Class I, III PCI LVDS, Bus-LVDS, LVPECL, RSDS - sys DSP™ Block (Lattice ECP™ Versions) - High performance multiply and accumulate - 4 to 10 blocks - 4 to 10 36x36 multipliers or - 16 to 40 18x18 multipliers or - 32 to 80 9x9 multipliers - Dedicated DDR Memory Support - Implements interface up to DDR400 (200MHz) - sys CLOCK™ PLLs - Up to 4 analog PLLs per device - Clock multiply, divide and phase shifting - Embedded and Distributed Memory - 18 Kbits to 645 Kbits sys MEM™ Embedded Block RAM (EBR) - Up to 163 Kbits distributed RAM - Flexible memory resources: - Distributed and block memory - System Level Support - IEEE Standard 1149.1 Boundary Scan, plus isp TRACY™ internal logic analyzer capability - SPI boot flash interface - 1.2V power supply - Low Cost FPGA - Features optimized for mainstream applications - Low cost TQFP and PQFP packaging - Flexible I/O Buffer - Programmable sys IO™ buffer supports wide range of interfaces: Table 1-1. Lattice ECP/EC Family Selection Guide Device PFU/PFF Rows PFU/PFF Columns PFUs/PFFs LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sys DSP Blocks LFEC1 12 16 192 1.5 6 18 2 - - 1.2 2 67 97 112 LFEC3 16 24 384 3.1 12 55 6 - - 1.2 2 67 97 145...