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MACH131SP - High-Performance EE CMOS Programmable Logic

Download the MACH131SP datasheet PDF. This datasheet also covers the MACH111SP variant, as both devices belong to the same high-performance ee cmos programmable logic family and are provided as variant models within a single manufacturer datasheet.

General Description

The MACH® 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing.

Key Features

  • x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™.
  • guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD x Configurable macrocells.
  • Programmable polarity.
  • Registered or combinatorial outputs.
  • Internal and I/O feedback paths.
  • D-type or T-type flip-flops.
  • Output Enabl.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MACH111SP_LatticeSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number MACH131SP
Manufacturer Lattice Semiconductor
File Size 633.04 KB
Description High-Performance EE CMOS Programmable Logic
Datasheet download datasheet MACH131SP Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MACH130-15 High-Density EE CMOS Programmable Logic Lattice
MACH130-20 High-Density EE CMOS Programmable Logic Lattice
MACH1 High-Performance EE CMOS Programmable Logic Lattice
MACH110-12 High-Density EE CMOS Programmable Logic Advanced Micro Devices
MACH110-12 High-Density EE CMOS Programmable Logic Lattice

Other Datasheets by Lattice Semiconductor

Part Number Description
MACH131 High-Performance EE CMOS Programmable Logic
MACH111 High-Performance EE CMOS Programmable Logic
MACH111SP High-Performance EE CMOS Programmable Logic
MACH211 High-Performance EE CMOS Programmable Logic
MACH211SP High-Performance EE CMOS Programmable Logic

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD x Configurable macrocells — Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops — Output Enables — Choice of clocks for each flip-flop — Input registers for MACH 2 family x JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available x Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.