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MACH231SP - High-Performance EE CMOS Programmable Logic

This page provides the datasheet information for the MACH231SP, a member of the MACH111SP High-Performance EE CMOS Programmable Logic family.

Datasheet Summary

Description

The MACH® 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing.

Features

  • x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™.
  • guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD x Configurable macrocells.
  • Programmable polarity.
  • Registered or combinatorial outputs.
  • Internal and I/O feedback paths.
  • D-type or T-type flip-flops.
  • Output Enabl.

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Datasheet preview – MACH231SP

Datasheet Details

Part number MACH231SP
Manufacturer Lattice Semiconductor
File Size 633.04 KB
Description High-Performance EE CMOS Programmable Logic
Datasheet download datasheet MACH231SP Datasheet
Additional preview pages of the MACH231SP datasheet.

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Full PDF Text Transcription

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MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD x Configurable macrocells — Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops — Output Enables — Choice of clocks for each flip-flop — Input registers for MACH 2 family x JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available x Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.
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