OR3T125 Datasheet PDF - Lattice Semiconductor (OR3xxx) 3C and 3T Field-Programmable Gate Arrays Specs

OR3T125 - (OR3xxx) 3C and 3T Field-Programmable Gate Arrays

This page provides the datasheet information for the OR3T125, a member of the OR3C80 (OR3xxx) 3C and 3T Field-Programmable Gate Arrays family.

Datasheet Summary

Description

FPGA Overview 7 PLC Logic 7 PIC Logic 8 System

Features

High-performance, cost-effective, 0.35 µm (OR3C) and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 µm). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation. ) Up to 186,000 usable gates. Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V.

Datasheet Details

Part number	OR3T125
Manufacturer	Lattice Semiconductor
File Size	3.47 MB
Description	(OR3xxx) 3C and 3T Field-Programmable Gate Arrays
Datasheet	OR3T125 Datasheet
Additional preview pages of the OR3T125 datasheet.

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Full PDF Text Transcription

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Data Sheet March 2002 ORCA® Series 3C and 3T Field-Programmable Gate Arrays Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm (OR3C) and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 µm). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation.) Up to 186,000 usable gates. Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance on OR3Txxx devices.

Published: Apr 26, 2006 |