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ORSO82G5 Datasheet PDF

Lattice Semiconductor ORSO82G5

the ORSO82G5 has eight channels of integrated 0.62.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces. With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, designers can build a configurable interface using proven backplane driver/receiver technology.
Part No. ORSO82G5
Datasheet ORSO82G5 Download
Manufacturer
Lattice Semiconductor
Description 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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ORSO82G5 datasheet page 1 preview

ABSOLUTE MAXIMUM RATINGS

..................................... 108 Recommended Operating Conditions ...................... 108 SERDES Electrical and Timing Characteristics ....... 108 High Speed Data Transmitter...................... 109 High Speed Data Receiver.......................... 110 External Reference Clock ........................... 112 Pin Descriptions ....................................................... 113 Power Supplies .................
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