ORSPI4
Overview
- OIF-SPI4-02.0 compliant interfaces Dynamic timing receive interface:
- Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades.
- Bit de-skewing up to 16 phases of the clock
- Capable of aligning bit-to-bit skews as large as ±1 bit periods Static timing receive interface:
- Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode
- Clock aligned or clock centered modes supported DIP-4 and DIP-2 parity generation and checking Transmit Interface:
- Speeds up to 450 MHz DDR (900 Mbits/s)
- Dedicated LVDS transmit interface for improved data eye integrity
- Automatic idle insertion 256 logical ports:
- Embedded Calendar-based sequence port polling mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar
