Lattice Semiconductor ORSPI4
the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip.| Part No. | ORSPI4 |
|---|---|
| Datasheet | ORSPI4 Download |
| Manufacturer |  Lattice Semiconductor |
| Description | Dual SPI4 Interface and High-Speed SERDES FPSC |
| Buy | Stock & Price |
FEATURES
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● OIF-SPI4-02.0 compliant interfaces Dynamic timing receive interface:
● Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades.
● Bit de-skewing up to 16 phases of the clock
● Capable of aligning bit-to-bit skews as large as ±1 bit periods Static timing receive interface:
● Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode
● Clock aligned or clock centered modes supported DIP-4 and DIP-2 parity generation and checking Transmit Interface:
● Speeds up to 450 MHz DDR (900 Mbits/s)
● Dedicated LVDS transmit interface for improved data eye integrity
● Automatic idle insertion 256 logical ports:
● Embedded Calendar-based sequence port polling mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar
● Up to 32 independent TX and 32 independent RX buffers per SPI4 interface internally. Various aggregation modes to support 1 to 32 separate embedded buffers per TX and RX
● Up to 4 independ...
