PALLV22V10Z Datasheet | Lattice Semiconductor

PALLV22V10 PALLV22V10Z 'L: -7/10/15 IND: -15 IND: -25 PALLV22V10 and PALLV22V10Z Families Low-Voltage (Zero Power) 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS x Low-voltage operation, 3.3 V JEDEC patible x x x x x x x x x GENERAL DESCRIPTION The PALLV22V10 is an advanced PAL® device built with low-voltage, high-speed, electricallyerasable CMOS technology. The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby current, the PALLV22V10Z allows battery powered operation for an extended period. The product terms are connected to the fixed OR array with a varied distribution from 8 to 16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or binatorial, and active high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell. Publication# 18956 Amendment/0 U SE The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. Rev: F Issue Date: September 2000 G N AL EW D D EV ES IC IG ES N F S O - VCC = + 3.0 V to 3.6 V mercial and industrial operating temperature range 7.5-ns t PD Electrically-erasable technology provides reconfigurable logic and full testability 10 macrocells programmable as registered or binatorial, and active high or active low to match application needs Varied product term distribution allows up to 16 product terms per output for plex functions Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability Extensive third-party software and programmer support 24-pin SKINNY DIP and 28-pin PLCC packages save space BLOCK DIAGRAM CLK/I0 1 11...