M430F149REV Datasheet | Lattice

.Data Sheet.co.kr High Performance E2CMOS® In-System Programmable Logic Features x High-performance, E2CMOS 3.3-V & 5-V CPLD families x Flexible architecture for rapid logic designs MACH 4 CPLD Family x x x x x x x x - Excellent First-Time-Fit TM and refit feature - Speed Locking TM performance for guaranteed fixed timing - Central, input and output switch matrices for 100% routability and 100% pin-out retention High speed - 7.5ns t PD mercial and 10ns t PD Industrial - 111.1MHz f CNT 32 to 256 macrocells; 32 to 384 registers 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages Flexible architecture for a wide range of design styles - D/T registers and latches - Synchronous or asynchronous mode - Dedicated input registers - Programmable polarity - Reset/ preset swapping Advanced capabilities for easy system integration - 3.3-V & 5-V JEDEC-pliant operations - JTAG (IEEE 1149.1) pliant for boundary scan testing - 3.3-V & 5-V JTAG in-system programming - PCI pliant (-7/-10/-12 speed grades) - Safe for mixed supply voltage system designs - Bus-Friendly TM inputs and I/Os - Programmable security bit - Individual output slew rate control Advanced E2CMOS process provides high-performance, cost-effective solutions Supported by isp Design EXPERTTM software for rapid logic development - Supports HDL design methodologies with results optimized for MACH 4 - Flexibility to adapt to user requirements - Software partnerships that ensure customer success Lattice and third-party hardware programming support - Lattice PROTM software for in-system programmability support on PCs and automated test equipment - Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# 17466 Amendment/0 Rev: M Issue Date: March 2000 Datasheet pdf -...