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MACH110-12 - High-Density EE CMOS Programmable Logic

General Description

The MACH110 is a member of our high-performance EE CMOS MACH 1 family.

This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed.

The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix.

Key Features

  • s may differ. O.

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Datasheet Details

Part number MACH110-12
Manufacturer Lattice
File Size 191.85 KB
Description High-Density EE CMOS Programmable Logic
Datasheet download datasheet MACH110-12 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCNT s 38 Inputs s 32 Outputs Lattice Semiconductor s 32 Flip-flops; 2 clock choices s 2 “PAL22V16” Blocks s Pin-compatible with MACH111, MACH210, MACH211, MACH215 GENERAL DESCRIPTION The MACH110 is a member of our high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells.