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MACHLV210-12 - High Density EE CMOS Programmable Logic

General Description

The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family.

This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell.

Key Features

  • l is chosen, one of two prod.

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Datasheet Details

Part number MACHLV210-12
Manufacturer Lattice
File Size 221.38 KB
Description High Density EE CMOS Programmable Logic
Datasheet download datasheet MACHLV210-12 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s Low-voltage operation, 3.3-V JEDEC compatible — VCC = +3.0 V to +3.6 V s < 5 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 Macrocells s 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT Lattice Semiconductor s 38 Bus-Friendly Inputs s 32 Outputs s 64 Flip-flops; 2 clock choices s 4 “PAL22V16” blocks with buried macrocells s Pin-, function-, and JEDEC-compatible with MACH210 s Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215 GENERAL DESCRIPTION The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family.