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iCE40 Datasheet Ultra-low Power Fpga And Sensor Manager

Manufacturer: Lattice

Overview: iCE40 LP/HX Family Data Sheet FPGA-DS-02029-3.7 March 2021 iCE40 LP/HX Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2018-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at .latticesemi./legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02029-3.7 iCE40 LP/HX Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 6 1.

Datasheet Details

Part number iCE40
Manufacturer Lattice
File Size 3.09 MB
Description Ultra-low power FPGA and sensor manager
Datasheet iCE40-Lattice.pdf

General Description

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7 1.1.

Key Features

  • 7 2. Product Family 8 3. Architecture9 3.1. Architecture Overview 9 3.1.1. PLB Blocks 10 3.1.2. Routing11 3.1.3. Clock/Control Distribution Network 11 3.1.4. sysCLOCK Phase Locked Loops (PLLs) 12 3.1.5. sysMEM Embedded Block RAM Memory 13 3.1.6. sysI/O 15 3.1.7. sysI/O Buffer 18 3.1.8. Non-Volatile Configuration Memory 19 3.1.9. Power On Reset 19 3.2. Programming and Configuration19 3.2.1. Power Saving Options 19 4. DC and Switching Characteristics 20 4.1. Absolute Maximum Ratings 20 4.2. Rec.

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