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iCE40 - Ultra-low power FPGA and sensor manager

Description

1.1.

Features

  • 7 2. Product Family 8 3. Architecture9 3.1. Architecture Overview 9 3.1.1. PLB Blocks 10 3.1.2. Routing11 3.1.3. Clock/Control Distribution Network 11 3.1.4. sysCLOCK Phase Locked Loops (PLLs) 12 3.1.5. sysMEM Embedded Block RAM Memory 13 3.1.6. sysI/O 15 3.1.7. sysI/O Buffer 18 3.1.8. Non-Volatile Configuration Memory 19 3.1.9. Power On Reset 19 3.2. Programming and Configuration19 3.2.1. Power Saving Options 19 4. DC and Switching Characteristics 20 4.1. Absolute Maximum Ratings 20 4.2. Rec.

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Datasheet Details

Part number iCE40
Manufacturer Lattice
File Size 3.09 MB
Description Ultra-low power FPGA and sensor manager
Datasheet download datasheet iCE40 Datasheet
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    iCE40 LP/HX Family Data Sheet FPGA-DS-02029-3.7 March 2021 iCE40 LP/HX Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same.
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