LTC4301L
Overview
- Level Translates 1V Signals to Standard 3.3V and 5V Logic Rails
- Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
- Bidirectional Buffer* for SDA and SCL Lines Increases Fanout
- Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane
- Isolates Input SDA and SCL Line from Output
- 10kV Human Body Model ESD Protection
- Supports Clock Stretching, Arbitration and Synchronization
- High Impedance SDA, SCL Pins for VCC = 0V
- CS Gates Connection from Input to Output
- Compatible with I2CTM, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation)
