LTC2274 Datasheet PDF | Linear Technology

Linear Technology LTC2274

The LTC2274 is perfect for demanding applications where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR). The encode clock inputs, ENC+ and ENC–, may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs.

Part No.	LTC2274
Datasheet	LTC2274 Download
Manufacturer	Linear Technology
Description	105Msps Serial Output ADC
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FEATURES

n High Speed Serial Interface (JESD204) n Sample Rate: 105Msps n 77.7dBFS Noise Floor n 100dB SFDR n SFDR >82dB at 250MHz (1.5VP-P Input Range) n PGA Front End (2.25VP-P or 1.5VP-P Input Range) n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Single 3.3V Supply n Power Dissipation: 1300mW n Clock Duty Cycle Stabilizer n Pin Compatible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272 n 40-Pin 6mm × 6mm QFN Package

APPLICATIONS

n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE LTC2274 16-Bit, 105Msps Serial Output ADC

DESCRIPTION

The LTC®2274 is a 105Msps, 16-bit A/D converter with a high speed serial interface. It is designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC Serial Interface for Data Converters speciﬁcation (JESD204). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance.