FEATURES
4-Channel Simultaneous Sampling ADC with Integrated, Fixed Gain, Differential Drivers n 68.3dB SNR n 78dB SFDR n Low Power: 1.27W Total, 318mW per Channel n 1.8V ADC Core and 3.3V Analog Input Supply n Serial LVDS Outputs: 1 or 2 Bits per Channel n Shutdown and Nap Modes n 11.25mm × 15mm BGA Package n DESCRIPTION
Each channel includes a lowpass filter between the driver output and ADC input. DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS and each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
Linear Technology
