LTC1749 Datasheet | Linear Technology

.. Features s s s s s s s s s s s s 12-Bit, 80Msps Wide Bandwidth ADC DESCRIPTIO The LTC®1749 is an 80Msps, 12-bit A/D converter designed for digitizing wide dynamic range signals up to frequencies of 500MHz. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry. The LTC1749 has a highly linear sample-and-hold circuit with a bandwidth of 500MHz. The SFDR is 80d B with an input frequency of 250MHz. Ultralow jitter of 0.15ps RMS allows undersampling of IF frequencies with minimal degradation in SNR. DC specs include ±1LSB INL and no missing codes. The digital interface is patible with 5V, 3V, 2V and LVDS logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate output power supply can be operated from 0.5V to 5V, making it easy to connect directly to low voltage DSPs or FIFOs. The 48-pin TSSOP package with a flow-through pinout simplifies the board layout. , LTC and LT are registered trademarks of Linear Technology Corporation. Sample Rate: 80Msps PGA Front End (2.25VP-P or 1.35VP-P Input Range) 71.8d B SNR and 87d B SFDR (PGA = 0) 70.2d B SNR and 87d B SFDR (PGA = 1) 500MHz Full Power Bandwidth S/H No Missing Codes Single 5V Supply Power Dissipation: 1.45W Two Pin Selectable Reference Values Data Ready Output Clock Pin patible 14-Bit 80Msps Device (LTC1750) 48-Pin TSSOP Package U APPLICATIO S s s s s s s s Direct IF Sampling Telemunications Receivers Cellular Base Stations Spectrum Analysis munications Test Equipment Undersampling BLOCK DIAGRA PGA AIN+ 80Msps, 12-Bit ADC with a 2.25V Differential Input Range OVDD 0.1µF S/H CIRCUIT 12-BIT PIPELINED ADC CORRECTION LOGIC AND SHIFT REGISTER 12 OUTPUT LATCHES - - - D11 D0 CLKOUT 0.5V TO 5V...