LTC2000 Datasheet | Linear Technology

Features n80d Bc SFDR at 70MHz f OUT n>68d Bc SFDR from DC to 1000MHz f OUT n40m A Nominal Full-Scale, ±1V Output pliant n10m A to 60m A Adjustable Full-Scale Current Range n Single or Dual Port DDR LVDS and DHSTL Interface n Low Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port) n>78d Bc 2-Tone IMD from DC to 1000MHz f OUT n - 165d Bc/Hz Additive Phase Noise at 1MHz Offset for 65MHz f OUT n170-Lead (9mm × 15mm) BGA Package Applications n Broadband munication Systems n DOCSIS CMTS n Direct RF Synthesis n Radar n Instrumentation n Automatic Test Equipment LTC2000 16-/14-/11-Bit 2.5Gsps DACs Description The LTC®2000 is a family of 16-/14-/11-bit 2.5Gsps current steering DACs with exceptional spectral purity. The single (1.25Gsps mode) or dual (2.5Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.25Gbps using a 625MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock. Additional Features such as pattern generation, LVDS loopout and junction temperature sensing simplify system development and testing. A serial peripheral interface (SPI) port allows configuration and read back of internal registers. Operating from 1.8V and 3.3V supplies, the LTC2000 consumes 2.2W at 2.5Gsps and 1.3W at 1.25Gsps. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 8330633. LVDS RECEIVERS DDR DATA FLIP-FLOPS SFDR (d Bc) Block Diagram TSTP/N JUNCTION TEMPERATURE PATTERN GENERATOR PD CS SCK SDI SDO SPI SVDD DAP/N[15:0] DBP/N[15:0] 4:1 16-BIT DAC IOUTP 50Ω 50Ω IOUTN DCKIP/N DCKOP/N AVDD18 DELAY ADJUST CLK DIVIDER ÷2 OR ÷4 DVDD18 AVDD33 CLOCK SYNC DVDD33 GAIN ADJUST CLK RECEIVER CKP/N 10k...