LTC2188 Datasheet | Linear Technology

Features n Two-Channel Simultaneously Sampling ADC n 77d B SNR n 90d B SFDR n Low Power: 76m W Total, 38m W per Channel n Single 1.8V Supply n CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: 1VP-P to 2VP-P n 550MHz Full Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Serial SPI Port for Configuration n 64-Lead (9mm × 9mm) QFN Package Applications nmunications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing LTC2188 16-Bit, 20Msps Low Power Dual ADC Description The LTC®2188 is a two-channel simultaneous sampling 16‑bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding munications applications with AC performance that includes 77d B SNR and 90d B spurious free dynamic range (SFDR). Ultralow jitter of 0.07ps RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.2LSBRMS. The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 1.8V VDD CH 1 ANALOG INPUT S/H 16-BIT ADC CORE CH 2 ANALOG INPUT 20MHz CLOCK S/H 16-BIT ADC CORE CLOCK CONTROL GND 1.8V OVDD OUTPUT DRIVERS D1_15 - - - D1_0 D2_15 - - - D2_0 CMOS, DDR CMOS OR...