LTC2208 Datasheet | Linear Technology

Features n Sample Rate: 130Msps n 78d BFS Noise Floor n 100d B SFDR n SFDR >83d B at 250MHz (1.5VP-P Input Range) n PGA Front End (2.25VP-P or 1.5VP-P Input Range) n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Optional Data Output Randomizer n LVDS or CMOS Outputs n Single 3.3V Supply n Power Dissipation: 1.25W n Clock Duty Cycle Stabilizer n Pin patible 14-Bit Version 130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) n 64-Pin (9mm × 9mm) QFN Package APPLICATIONS n Telemunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 16-Bit, 130Msps ADC DESCRIPTION The LTC®2208 is a 130Msps, sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end. The LTC2208 is perfect for demanding munications applications, with AC performance that includes 78d BFS Noise Floor and 100d B spurious free dynamic range (SFDR). Ultra low jitter of 70fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. TYPICAL APPLICATION VCM 2.2μF 1.25V MON MODE BIAS VOLTAGE 3.3V...