LTC2231 Datasheet | Linear Technology

Features - Sample Rate: 170Msps/135 Msps - 61d B SNR up to 140MHz Input - 75d B SFDR up to 200MHz Input - 775MHz Full Power Bandwidth S/H - Single 3.3V Supply - Low Power Dissipation: 890m W/660m W - LVDS, CMOS, or Demultiplexed CMOS Outputs - Selectable Input Ranges: ±0.5V or ±1V - No Missing Codes - Optional Clock Duty Cycle Stabilizer - Shutdown and Nap Modes - Data Ready Output Clock - Pin patible Family 185Msps: LTC2220-1 (12-Bit) 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) - 64-Pin 9mm x 9mm QFN Package U APPLICATIO S - Wireless and Wired Broadband munication - Cable Head-End Systems - Power Amplifier Linearization - munications Test Equipment , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. LTC2230/LTC2231 10-Bit,170Msps/ 135Msps ADCs DESCRIPTIO The LTC®2230 and LTC2231 are 170Msps/135Msps, sampling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2230/ LTC2231 are perfect for demanding munications applications with AC performance that includes 61d B SNR and 75d B spurious free dynamic range for signals up to 200MHz. Ultralow jitter of 0.15ps RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.12LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC- inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer...