LTC2271 Datasheet | Linear Technology

Features n 2-Channel Simultaneous Sampling ADC n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel n 84.1d B SNR (46μVRMS Input Referred Noise) n 99d B SFDR n Low Power: 185m W Total n 92m W per Channel n Single 1.8V Supply n Selectable Input Ranges: 1VP-P to 2.1VP-P n 200MHz Full-Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n Pin patible With LTC2190: 16-Bit, 25Msps, 104m W n 52-Lead (7mm × 8mm) QFN Package APPLICATIONS n Low Power Instrumentation n Software-Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition 16-Bit, 20Msps Serial Low Noise Dual ADC DESCRIPTION The LTC®2271 is a 2-channel, simultaneous sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding munications applications with AC performance that includes 84.1d B SNR and 99d B spurious free dynamic range (SFDR). DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ) and no missing codes over temperature. The transition noise is 1.44LSBRMS. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC- inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION CH1 ANALOG S/H INPUT CH2 ANALOG S/H INPUT ENCODE INPUT 1.8V VDD 16-BIT ADC CORE 16-BIT ADC CORE 1.8V OVDD DATA SERIALIZER OGND 2271 TA01 OUT1A OUT1B OUT1C OUT1D OUT2A OUT2B OUT2C OUT2D DATA CLOCK OUT FRAME SERIALIZED LVDS OUTPUTS INL ERROR...