LTC2273 Datasheet | Linear Technology

Features n High Speed Serial Interface (JESD204) n Sample Rate: 80Msps/65Msps n 77.7d BFS Noise Floor n 100d B SFDR n SFDR >90d B at 140MHz (1.5VP-P Input Range) n PGA Front End (2.25VP-P or 1.5VP-P Input Range) n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Single 3.3V Supply n Power Dissipation: 1100m W/990m W n Clock Duty Cycle Stabilizer n Pin patible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272 n 40-Pin 6mm × 6mm QFN Package APPLICATIONS n Telemunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE LTC2273/LTC2272 16-Bit, 80Msps/65Msps Serial Output ADC DESCRIPTION The LTC®2273/LTC2272 are 80Msps/65Msps, 16-bit A/D converters with a high speed serial interface. They are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC serial interface for data converters specification (JESD204). The LTC2273/LTC2272 are perfect for demanding applications where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7d B Noise Floor and 100d B spurious free dynamic range (SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature. The encode clock inputs, ENC+ and ENC- , may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION VCM 2.2μF 1.25V MON MODE BIAS VOLTAGE 3.3V SENSE INTERNAL...