LTC4301L Datasheet | Linear Technology

Features - Level Translates 1V Signals to Standard 3.3V and 5V Logic Rails - Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN - Bidirectional Buffer- for SDA and SCL Lines Increases Fanout - Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane - Isolates Input SDA and SCL Line from Output - 10k V Human Body Model ESD Protection - Supports Clock Stretching, Arbitration and Synchronization - High Impedance SDA, SCL Pins for VCC = 0V - CS Gates Connection from Input to Output - patible with I2CTM, I2C Fast Mode and SMBus Standards (Up to 400k Hz Operation) - Small 8-Pin MSOUP and DFN (3mm × 3mm) Packages APPLICATIO S - Hot Board Insertion - Servers - Capacitance Buffer/Bus Extender - Desktop puters Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation DESCRIPTIO The LTC®4301L hot swappable, 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. In addition, the LTC4301L SDAIN and SCLIN pins are patible with systems with pull-up voltages as low as 1V. Control circuitry prevents the backplane from being connected to the card until a stop bit or a bus idle is present. When the connection is made, the LTC4301L provides bidirectional buffering, keeping the backplane and card capacitances isolated. When driven low, the CS input pin allows the part to connect after a stop bit or bus idle occurs. Driving CS high breaks the connection between SCLIN and SCLOUT and between SDAIN and SDAOUT. A logic high on READY indicates that the backplane and card sides are connected together. The LTC4301L is offered in 8-pin DFN (3mm × 3mm) and MSOP packages. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7032051. TYPICAL APPLICATIO 1.2V VCC SDA µP SCL 3.3V...