F60C1A0004-M7 Key Features
- Density: 4G bits
- Organization
- Package
- Power supply VDD/VDDQ =1.35V (1.283 to 1.45V)
- Differential clock inputs (CK and CK#)
- DLL aligns DQ and DQS transitions with CK
- Data Rate
- 2KB page size (x16)
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data