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MX23L6430 - 64M-Bit Synchronous Mask ROM

Description

The 64M synch.

MROM is a synchronous high bandwidth mask programmable ROM with MXIC's high performance CMOS process technology and is organized either as 4M x 16 bits or 2M x 32 bits depending on polarity of WORD pin.

Features

  • Switchable organization : 4M x 16 ( word mode ) or 2M x 32 ( double word mode ).
  • Power supply 3.0V ~ 3.6V.
  • TTL compatible with multiplexed address.
  • All inputs are sampled at rising edge of system clock.
  • Read performance : - 4-1-1-1@33MHz(RAS Latency=1, CAS Latency=3 ) - 5-1-1-1@50MHz(RAS Latency=1, CAS Latency=4 ) - 7-1-1-1@66MHz(RAS Latency=2, CAS Latency=5 ) - 7-1-1-1@100MHz(RAS Latency=2, CAS Latency=5) - Clock to valid output delay (tSAC) : 6ns(.

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Datasheet Details

Part number MX23L6430
Manufacturer Macronix
File Size 151.46 KB
Description 64M-Bit Synchronous Mask ROM
Datasheet download datasheet MX23L6430 Datasheet

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Full PDF Text Transcription

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INDEX PRELIMINARY MX23L6430 64M-Bit Synchronous Mask ROM FEATURES • Switchable organization : 4M x 16 ( word mode ) or 2M x 32 ( double word mode ) • Power supply 3.0V ~ 3.6V • TTL compatible with multiplexed address • All inputs are sampled at rising edge of system clock • Read performance : - 4-1-1-1@33MHz(RAS Latency=1, CAS Latency=3 ) - 5-1-1-1@50MHz(RAS Latency=1, CAS Latency=4 ) - 7-1-1-1@66MHz(RAS Latency=2, CAS Latency=5 ) - 7-1-1-1@100MHz(RAS Latency=2, CAS Latency=5) - Clock to valid output delay (tSAC) : 6ns(Max.) • MRS cycle with address key programs : - RAS Latency : 1 & 2 - CAS Latency : 2 ~ 8 - Burst Length : 8 double word - Burst Type : Sequential or Interleaved • DQM for data-out masking • Package : 86 pin TSOP(II) GENERAL DESCRIPTION The 64M synch.
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