Description
The MT28C3212P2FL and MT28C3212P2NFL combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium.
Features
- Flexible dual-bank architecture.
- Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa.
- Organization: 2,048K x 16 (Flash) 128K x 16 (SRAM).
- Basic configuration: Flash Bank a (4Mb Flash for data storage).
- Eight 4K-word parameter blocks.
- Seven 32K-word blocks Bank b (28Mb Flash for program storage).
- Fifty-six 32K-word main blocks SRAM 2Mb.
MT28C3212P2 Datasheet
