MX26L12811MC Datasheet | Macronix

FEATURES - 3.0V to 3.6V operation voltage - Block Structure - 128 x 128Kbyte Erase Blocks - Fast random / page mode access time - 120/25 ns Read Access Time (page depth:4-word) - 32-Byte Write Buffer .. - 6 us/byte Effective Programming Time - High Performance - Block erase time: 2s typ. - Byte programming time: 210us typ. - Block programming time: 0.8s typ. (using Write to Buffer mand) - Program/Erase Endurance cycles: 10 cycles Packaging Performance - Low power dissipation - typical 15m A active current for page mode read - 80u A/(max.) standby current - 44-Lead SOP Technology - Nbit (0.25u) MTP Technology GENERAL DESCRIPTION The MXIC's MX26L12811MC series MTP use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density MTP memory solution with reliable performance and most cost-effective. The device organized as by 8 bits or by 16 bits of output bus. The device is packaged in 44-Lead SOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The device offers fast access time and allowing operation of high-speed microprocessors without wait states. The device augment EPROM functionality with in-circuit electrical erasure and programming. The device uses a mand register to manage this functionality. The MXIC's Nbit technology reliably stores memory contents even after the specific erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's character to trap or release charges from ONO layer. The device uses a 3.0V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. P/N:PM0990 REV. 1.0, OCT. 29, 2003 PIN CONFIGURATION 44-SOP (for word...