MX25L5121E
Description
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Key Features
- Serial Peripheral Interface compatible -- Mode 0 and Mode 3
- 512K: 524,288 x 1 bit structure 1M: 1,048,576 x 1 bit structure
- 16 Equal Sectors with 4K bytes each (512Kb) 32 Equal Sectors with 4K bytes each (1Mb) - Any Sector can be erased individually
- 1 Equal Blocks with 64K byte each (512Kb) 2 Equal Blocks with 64K byte each (1Mb) - Any Block can be erased individually
- Program Capability - Byte base - Page base (32 bytes)
- Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
- Latch-up protected to 100mA from -1V to Vcc +1V
