MN103S33N Datasheet | Matsushita Electric

.. Type mand ROM (× 64-bit) Data RAM (× 32-bit) Package Minimum Instruction Execution Time Interrupts MN103S33N 512 K-byte 24 K-byte MBGA360-C-1313A - Lead-free 24.3 ns (at 2.3 V to 2.7 V, 41 MHz) - RESET - IRQ × 15 - NMI - Key input - Timer × 44 - Input capture × 16 - PWM × 8 - SIF × 25 - DMA × 12 - WDT - A/D - System error 8-bit timer × 12 Reload-down count Cascade connection possible (usable as a 16-bit to 32-bit timer) 8-bit timer with PWM × 8 Reload-down count Cascade connection possible (usable as a 16-bit to 32-bit timer) PWM generating function 16-bit timer × 6 Up-down count Input capture function PWM generating function pare/capture register 2-ch. 16-bit timer × 6 Reload-down count Watchdog timer × 1 DMA Controller Number of channels: 4 Unit of transfer: 8/16/32 bits Max. Transfer cycles: 65535 Staring factor: external interrupt, timer factor, PWM factor, serial transmission/reception factor, A/D conversion finish, software factor Transfer method: 2-bus cycle transfer Adressing modes: fixed, increment, decrement Transfer modes: word transfer, burst transfer, intermittent transfer Serial 0, 1, 3 to 8, A, B: start-stop synchronization/synchronization/I2C monly used, 10 lines Serial 2, 9: 2 lines for start-stop synchronization only, serial 2: 10 bytes containing receive FIFO - mon use Serial Interface I/O Pins Input A/D Inputs PWM ICR OCR Timer Synchronous Output ROM Collection Pl 25 4-ch. I/O 10-bit × 25-ch. 12-, 14-bit resolution × 5-ch. output waveform value load control function provided 16-bit resolution × 2-ch. 28-bit × 13-ch. + 16-bit × 6-ch. (mon with timer) 16-bit × 12-ch. (mon with timer) 4-bit (synchronous output) × 2-ch. ea s ht e v tp is :// it pa fo na llo so win ni g c. U co R .jp L a /s bo em u ic t la on te /e st -in in de for x. ma ht t m ion l . - mon use MAF00005GEM M Di ain sc te on na tin nc ue e/ d Timer Counter .. Pin Assignment Perspective PF3, PF1, PD5, VDD2 PD2, N.D. N.D....