ST16C554 Datasheet | MaxLinear

Description The ST16C554, ST16C554D and ST68C554 are each quad Universal Asynchronous Receivers and Transmitters (UARTs) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels, and data rates of up to 1.5Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The ST16C554 is available in a 64-pin LQFP package, the ST16C554D is available in both a 64-pin LQFP and a 68-pin PLCC package, and the ST68C554 is available in a 68-pin PLCC package. The 64-pin package only offers the 16 mode interface, but the 68-pin package offers an additional 68 mode interface which allows easy integration with Motorola processors. The ST16C554CQ64 (64-pin) offers three-state interrupt output while the ST16C554DCQ64 provides continuous interrupt output. The ST16C554 and ST16C554D bine the package interface modes of the 16C554 and 68C554 on a single integrated chip. Ordering Information - page 32 Features - Pin-to-pin patible with the industry standard ST16C454, ST68C454, ST68C554, TI’s TL16C554A and Philips’ SC16C554B - Intel or Motorola data bus interface select - Four independent UART channels  Register set patible to 16C550  Data rates of up to 1.5Mbps at 5V  Data rates of up to 500kbps at 3.3V  16 byte transmit FIFO  16 byte receive FIFO with error tags  4 selectable RX FIFO trigger levels  Full modem interface - 2.97V to 5.5V supply operation - Crystal oscillator or external clock input Applications - Portable appliances - Telemunication network routers - Ethernet network routers - Cellular data devices - Factory automation and process controls Block Diagram A2:A0 D7:D0 IOR# IOW# CSA# CSB# CSC# CSD# INTA INTB INTC INTD TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL Data Bus Interface UART Channel A UART Regs BRG 16 Byte TX FIFO TX & RX IR ENDEC 16 Byte RX FIFO UART Channel B...