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DS33R41 - Inverse-Multiplexing Ethernet Mapper

General Description

The DS33R41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four interleaved T1/E1/J1 lines using a robust, balanced, and programmable inverse multiplexing.

Key Features

  • 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control Layer 1 Inverse Multiplexing Over Four T1/E1/J1 Lines Through the Integrated Framers and LIUs Supports Up to 7.75ms Differential Delay Aggregate Bandwidth from Up to Four T1/E1/J1 Links T1/E1 Signaling Capability for OAM HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill CIR Controller Provides Fractional Allocations in 512kbps Increments Programmable BERTs External 16MB, 100MHz SDRAM Buffering.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION The DS33R41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four interleaved T1/E1/J1 lines using a robust, balanced, and programmable inverse multiplexing. Four integrated T1/E1/J1 transceivers provide framing and line interfacing functionality. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in committed information rate (CIR) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. FEATURES 10/100 IEEE 802.