DS34T101 Datasheet | Maxim Integrated

.. Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE SATo P/CESo PSN/TDMo IP/HDLC draft-pliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or MPLS packet network. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. This eliminates the need for remote timing sources in cabinets and pedestals. The Ethernet side of the DS34T108 provides high Qo S capabilities to its MII/RMII/SSMII port, while the WAN side supports full-featured T1/E1 framers and LIUs. This takes the solution all the way through analog, while preserving options to make use of TDM streams at key intermediate points. The high level of integration that the DS34T108 brings minimizes cost, board space, and time to market. Features - - - - - - - - - - - - - - - - Full-Featured T1/E1/J1 LIU/Framer/TDM-Over Packet Supports Adaptive Clock Recovery, mon Clock (Using RTP), External Clock, and Loopback Timing Modes Selectable 32-Bit or 16-Bit Processor Bus Clock Rate Adapter for T1/E1 Master Clock 10/100 Ethernet MAC That Supports MII/RMII/SSMII Fully patible with IEEE 802.3 Standard VLAN Support According to 802.1 p&Q Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, and Metro Ethernet End-to-End TDM Synchronization Through the IP/MPLS Domain by Eight Independent On-Chip TDM Clock Recovery Mechanisms Single Serial Support for RS-530 and V.35 Single DS3/E3/STS-1 to Ethernet Packet Loss pensation and Handling of Misordered Packets 64 Independent Bundle/Connections Glueless SDRAM Buffer Management 1.8V Core, 3.3V I/O plies with IETF PWE3 RFCs and Drafts for CESo PSN, SATo P, TDMo IP, and HDLC Applications TDM Circuit Extension Over PSN o Leased- Line Services Over PSN o TDM Over G/E- PON o TDM Over Cable o TDM Over Wi MAX Cellular Backhaul Over PSN Multiservice Over...