DS38464 Datasheet | Maxim Integrated

FEATURES - - - - - - - - - 2Mbits organized as a 64K x 40 memory 6 years minimum data retention in the absence of external power Nonvolatile circuitry transparent to and independent of host system Automatic write protection circuitry safeguards against data loss Battery monitor checks remaining capacity daily Fast access time of 70ns Operating VCC range of 3.0V to 3.6V Employs popular JEDEC standard 72position SIMM connector Operating temperature: 0o C to +70o C PIN ASSIGNMENT PIN DESCRIPTION A0 - A15 DQ0 - DQ39 CEA WE OE VCC GND Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Inputs Output Enable Inputs 3.3V Power Supply Ground DS38464 72-PIN SIMM 1 of 10 DESCRIPTION The DS38464 is a self-contained 2,621,440-bit, nonvolatile static RAM, which is organized as a 64K x 40 memory. Built using three 64K x 16 SRAMs, one nonvolatile control IC, and one lithium battery, this nonvolatile memory contains all the necessary control circuitry and lithium energy source to maintain data integrity in the absence of power for more than 6 years. The DS38464 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry. READ MODE The DS38464 executes a read cycle whenever WE is inactive (high) and CE and OE are active (low). The unique address specified by the 16 address inputs (A0 - A15) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either t CO for CE or t OE for OE rather than t ACC. WRITE MODE The DS38464 executes a write cycle whenever both WE and CE signals are in the active (low) state after address inputs are stable. The later occurring...