Datasheet Summary
19-3550; Rev 0; 1/05
Delay Lines for High-Speed Clock Distribution Systems
General Description
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Features
- Supports HSTL Source Terminated Lines
- All-Passive Design
- patible with 100Ω Differential and 50Ω SingleEnded Transmission Lines
- Small 3mm x 3mm Package
The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a...