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MAX3991 - 10Gbps Clock and Data Recovery

General Description

The MAX3991 is a 10Gbps clock and data recovery (CDR) with limiting amplifier IC for XFP optical receivers.

The MAX3991 and the MAX3992 (CDR with equalizer) form a signal conditioner chipset for use in XFP transceiver modules.

Key Features

  • Multirate Operation from 9.95Gbps to 11.1Gbps.
  • 7mVP-P Input Sensitivity (BER ≤ 10-12).
  • 0.6UIP-P Total High-Frequency Jitter Tolerance.
  • Low-Output Jitter Generation: 7mUIRMS.
  • Low-Output Deterministic Jitter: 4.6psP-P.
  • XFI-Compliant Output Interface.
  • LOS Indicator with Programmable Threshold.
  • LOL Indicator.
  • Power Dissipation: 350mW MAX3991 Ordering Information PART MAX3991UTG MAX3991UTG+.
  • TEMP RANGE 0°C to +85°.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-3486; Rev 0; 11/04 www.DataSheet4U.com 10Gbps Clock and Data Recovery with Limiting Amplifier General Description The MAX3991 is a 10Gbps clock and data recovery (CDR) with limiting amplifier IC for XFP optical receivers. The MAX3991 and the MAX3992 (CDR with equalizer) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps. The MAX3991 has 7mVP-P input sensitivity (BER ≤ 10-12), which allows direct connection to a transimpedance amplifier without the use of a stand-alone limiting amplifier. The phase-locked loop (PLL) is optimized for jitter tolerance and provides 0.6UI of high-frequency tolerance in SONET, Ethernet, and Fibre-Channel applications.