GENERAL DESCRIPTION
On each of its four input clocks and eight output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The best input clock is selected, manually or automatically, as the reference clock for each of the two flexible, high-performance digital PLLs. Each DPLL lock to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLLs are followed by a clock synthesis subsystem that has four fully programmable digital frequency synthesis blocks, two high-speed lowjitter APLLs, and eight output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS. For telecom systems, the DS31404 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31404 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813, and G.8262.
Maxim Integrated
