GENERAL DESCRIPTION
The built-in Committed Information Rate (CIR) controllers provide fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33Z44 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode. FEATURES
§ Four 10/100 IEEE 802.3 Ethernet MACs (MII and RMII) Half/Full Duplex with Automatic Flow Control Four 52Mbps Synchronous TDM Serial Ports with independent transmit and receive timing. HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill Committed Information Rate Controllers Provide Fractional Allocations in 512kbps Increments Programmable BERT for Serial (TDM) Interfaces External 16MB, 100MHz SDRAM Buffering Parallel Microprocessor Interface SPI Interface and Hardware Mode for Operation Without a Host Processor 1.8V Operation with 3.3V Tolerant I/O IEEE 1149.1 JTAG Support § § § § § § § § § APPLICATIONS
Transparent LAN Service LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 FUNCTIONAL DIAGRAM DS33Z44 TRANSCEIVERS/ SERIAL DRIVERS FEATURES
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Maxim Integrated
